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| FPGA代做|使用verilog语言实现sobel边缘提取算法 |
| 来源：本站 日期：2018/5/4 浏览量：2348 |
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功能描述：
module sobel_get(
i_clk,
i_rst,
i_median,
o_CLK9dix,
o_Sobel_data
);
input i_clk;
input i_rst;
input[7:0] i_median;
output o_CLK9dix;
output[7:0]o_Sobel_data;
wire[7:0]z11;
wire[7:0]z12;
wire[7:0]z13;
wire[7:0]z21;
wire[7:0]z22;
wire[7:0]z23;
wire[7:0]z31;
wire[7:0]z32;
wire[7:0]z33;
reg CLK9dix;
reg[3:0]count;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
count <= 4'd0;
else begin
if(count >= 4'd9)
count <= 1;
else
count <= count + 1;
end
end
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
CLK9dix <= 1'd0;
else begin
if(count >= 4'd9)
CLK9dix <= 1'd1;
else
CLK9dix <= 1'd0;
end
end
integer i;
reg[7:0]men_delay[300:1];
always @(posedge CLK9dix or posedge i_rst)
begin
if(i_rst)
begin
for(i=1;i<=300;i=i+1)
men_delay[i]<=8'd0;
end
else begin
men_delay[1]<=i_median;
for(i=2;i<=300;i=i+1)
men_delay[i]<=men_delay[i-1];
end
end
assign z11 = men_delay[1];
assign z12 = men_delay[2];
assign z13 = men_delay[3];
assign z21 = men_delay[1+80];
assign z22 = men_delay[2+80];
assign z23 = men_delay[3+80];
assign z31 = men_delay[1+80+80];
assign z32 = men_delay[2+80+80];
assign z33 = men_delay[3+80+80];
reg[11:0] ZZ1;
reg[10:0]ZZ11;
reg[10:0]ZZ12;
always @(posedge CLK9dix or posedge i_rst)
begin
if(i_rst)
begin
ZZ1 <= 12'd0;
ZZ11 <= 11'd0;
ZZ12 <= 11'd0;
end
else begin
ZZ11 <= z11 + 2*z21 + z31;
ZZ12 <= z13 + 2*z23 + z33;
if(ZZ11 >= ZZ12)
ZZ1 <= ZZ11 - ZZ12;
else
ZZ1 <= ZZ12 - ZZ11;
end
end
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